用Verilog設計一個5分頻器

時間:2017-10-10 13:30:28

 5分頻,奇數分頻都可以類似這么做,只需要改div1和div2的參數。div1為奇數分頻除2的余數。采用上升延和下降延分別觸發不同波形,最后疊加的方式產生奇數分頻。


:module divfreq(clk, clk1x, rst, clk1xpose, clk1xnege, coutpose, coutnege);
input clk;
input rst;
output clk1x;
output clk1xpose;
output clk1xnege;
output[2:0] coutpose;
output[2:0] coutnege;
reg clk1xpose;
reg clk1xnege;
reg[2:0] coutpose;
reg[2:0] coutnege;
parameter div1 = 2 , div2 = 4;  // div1 = 5 / 2, div2 = 5 - 1
assign clk1x = clk1xpose | clk1xnege;
[email protected](posedge clk or negedge rst)
 begin
  if(!rst)
  
    clk1xpose = 0;
 
  else if(coutpose == div1)
    clk1xpose = ~clk1xpose;
  else if(coutpose == div2)
    clk1xpose = ~clk1xpose;
  else 
    clk1xpose = clk1xpose;
 end
[email protected](negedge clk or negedge rst)
 begin
  if(!rst)
  
    clk1xnege = 0;
 
  else if(coutnege == div1)
   clk1xnege = ~clk1xnege;
  else if(coutnege == div2)
   clk1xnege = ~clk1xnege;
  else 
   clk1xnege = clk1xnege;
 end
[email protected](posedge clk or negedge rst)
 begin
  if(!rst)
   coutpose = 0;
  else if(coutpose == div2)
   coutpose = 0;
  else
   coutpose = coutpose + 1;
 end
[email protected](negedge clk or negedge rst)
 begin
  if(!rst)
   coutnege = 0;
  else if(coutnege == div2)
   coutnege = 0;
  else
   coutnege = coutnege + 1;
 end
endmodule

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